Semiconductor transistors comprise the backbone of integrated circuits. Field-effect transistors (FETs) or metal-oxide semiconductor field-effect transistors (MOSFETs) are the most common transistors. Silicide formation over the source/drain regions and/or gate electrode provide the advantages of lowering the resistivity of the FET formed, improves the FET's performance, and provides a contact region. It is desirable to have sufficiently thick silicide layers over the source/drain regions to lower resistivity while also having a shallow junction below the silicide layers.
U.S. Pat. No. 5,843,826 to Hong describes a method of forming a FET that occupies a reduced surface area on a substrate because is incorporates elevated source/drain contacts provided at least partially over the field oxide regions. A conventional self-aligned silicide (salicide) process is used to form a titanium silicide or other metal silicide over the gate electrode and over the source/drain regions and the elevated poly structures over the field oxide regions.
U.S. Pat. No. 5,858,848 to Gardner et al. describes a method of forming self-aligned nitride sidewall spacers between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. A metal salicide may be formed over the source/drain and gate electrode.
U.S. Pat. No. 5,874,341 to Gardner et al. describes a method of forming an insulated-gate field-effect transistor (IGFET), such as a MOSFET, with a gate electrode in a trench, i.e. a trench transistor, and a source contact in the trench. Titanium suicides are formed on sidewall source/drain regions, gate electrode and the contact portion of the bottom surface within the trench.
U.S. Pat. No. 5,879,998 to Krivokapic describes a method of manufacturing very short channel length devices having source and drain regions in a substrate and a gate region on the top surface of the substrate between the source/drain regions. A silicide layer is used to establish separate local interconnect layers from the source and drain regions to respective source and drain metal contacts.
U.S. Pat. No. 5,918,130 to Hause et al. describes a method for fabricating a transistor by forming a silicide layer across the source/drain regions before formation of the gate conductor. A polycide layer is formed over the poly gate conductor.